80KSBR200 Datasheet, PDF (63/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
8.0 Registers
The registers of the SerB are grouped into functions. Register types include the following:
◆ _{sRIO Registers (CARs and CSRs)}
◆ _{SerB Configuration Registers}
◆ _{SerB Error Counter Registers}
◆ _{SERDES Control Registers}
◆ _{Flag & Flag Mask Registers}
In the sRIO world, the term CSR is used for “Command and Status Registers”. These are the combination of the config-
uration and flag registers.
All registers are accessible by S-Port, I²C and JTAG. Not all parts of the registers are necessarily accessed from all
parts. The programming of the configuration registers are described in the section on system initialization. When using
sRIO, the configuration registers are accessible only through maintenance packets. They cannot be accessed by using
NWRITE, NREAD or SWRITE.
As a further grouping, the electrical characteristics of the ports and presence of external memory should remain fixed
once configured, so these should be separated from configurations that may change. It is more likely that destination IDs
and other soft configurations will change, especially in large applications that are not adequately served by four output
queues on a port.
The configuration registers are broken into blocks of related functions that may be read by any port and written by any
port that will not kill itself in process.
It should be noted that in addition to the registers shown here, others exist that are described elsewhere and in the
sRIO specification. An example is the Error Management registers that may be found in the RapidIO Part 8: Error Manage-
ment Extension Specification and in the “Error Handling” section of this document.
8.1 sRIO Registers
This chapter describes the visible register set that allows an external processing element to determine the capabilities,
configuration, and status of a processing element using this logical specification. All registers are 32-bits and aligned to a
32-bit boundary.
8.1.1 Register Summary
Table below shows the register map for this RapidIO specification. These capability registers (CARs) and command
and status registers (CSRs) can be accessed using RapidIO maintenance operations. Any register offsets not defined are
considered reserved for this specification unless otherwise stated. Other registers required for a processing element are
defined in other applicable RapidIO specifications and by the requirements of the specific device and are beyond the
scope of this specification. Read and write accesses to reserved register offsets shall terminate normally and not cause an
error condition in the target device. Writes to CAR (read-only) space shall terminate normally and not cause an error condi-
tion in the target device.
8.1.2 Extended Features Data Structure
The RapidIO capability and command and status registers implement an extended capability data structure. If the
extended features bit (bit 28) in the processing element features register is set, the extended features pointer is valid and
points to the first entry in the extended features data structure. This pointer is an offset into the standard 16 Mbyte capa-
bility register (CAR) and command and status register (CSR) space and is accessed with a maintenance read operation in
the same way as when accessing CARs and CSRs.
The extended features data structure is a singly linked list of double-word structures. Each of these contains a pointer
to the next structure (EF_PTR) and an extended feature type identifier (EF_ID). The end of the list is determined when the
next extended feature pointer has a value of logic 0. All pointers and extended features blocks shall index completely into
the extended features space of the CSR space, and all shall be aligned to a double-word boundary so the three least
significant bits shall equal logic 0. Pointer values not in extended features space or improperly aligned are illegal and shall
be treated as the end of the data structure.
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March 19, 2007
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