80KSBR200 Datasheet, PDF(6/172 Page) Integrated Device Technology

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80KSBR200 Datasheet, PDF (6/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

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IDT 80KSBR200

Notes

Table 55: Lost Packet Replacement Register

Table 56: Source and Destination ID Register

Table 57: PAE / PAF Register

Table 58: Watermark Register

Table 59: Waterlevel Register

Table 60: Space Available Register

Table 61: MBIST Control Register

Table 62: QBIST Control Register

Table 63: JTAG Device ID Register

Table 64: Case Scenario Packet Header Register

Table 65: Case Scenario Start Address Register

Table 66: Case Scenario Next Address Register

Table 67: Case Scenario Stop Address Register

Table 68: Case Scenario Frame Register

Table 69: Missing Packet Start Address Register

Table 70: Missing Packet Current Address Register

Table 71: Missing Packet Address Increment Register

Table 72: Missing Packet Stop Address Register

Table 73: Data Packet Interval Timer Register

Table 74: Doorbell Packet Interval Timer Register

Table 75: Missing Packet Size Register

Table 76: Missing Packet Address Logging Register

Table 77: Missing Packet Address Logging Register for TI DSP

Table 78: S-Port Data Packet Received Counter

Table 79: S-Port Data Packet Transmitted Counter

Table 80: S-Port Priority Packet Received Counter

Table 81: S-Port Priority Packet Transmitted Counter

Table 82: S-Port Packet Received Counter

Table 83: S-Port Packet Transmitted Counter

Table 84: SERDES Quad Control Register

Table 85: Flag and Flag Mask Register

Table 86: S-Port Link Status Register

Table 87: Device Configuration Error Register

Table 88: sRIO DMA Status Register

Table 89: Missing Packet Flag Register

Table 90: FIFO Queue Empty Flag Register

Table 91: FIFO Queue Full Flag Register

Table 92: DSP Interrupt Flag Register

Table 93: Tally Doorbell Flag Register

Table 94: Missing Packet Programmable Flag Register

Table 95: Port Speed Selection Pin Values

Table 96: Input Reference Clock Jitter Specification

Table 97: Absolute Maximum Ratings

Table 98: Recommended Temperature and Operating Voltage

Table 99: AC Test Conditions (Vdd3 = 3.3V / 2.5V); JTAG, I2C, RST

Table 100: Typical Power Figures

Table 101: I2C Static Address Selection Pin Configuration

Table 102: P-Port AC Electrical Characteristics

Table 103: JTAG Pin Description

Table 104: Instructions Supported by 80KSBR200âs JTAG Boundary Scan

Table 105: System Controller Device ID Register

Table 106: System Controller Device ID Instruction Format

Table 107: Data Stream for JTAG Configuration Register Access Mode

Table 108: Pin Listings

Advanced Datasheet*

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March 19, 2007

â2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a

Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.

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