80KSBR200 Datasheet, PDF (66/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Note:
1. The above register is described in the RIO Specification Part 1, sec. 5.4.4
Advanced Datasheet*
Processing Element Features CAR
PEFCAR identifies the major functionality provided by the processing element.
PEFCAR is a read only register.
Name: PROC_ELE_FEAT_CAR Address: 0x00010
Bit
2:0
3
4
5
6
7
8
9
10
18:11
19
23:20
27:24
28
29
30
31
Field Name
Reset
Value
Comment
EXT_ADDR_SUP 3b001
EXT_FEAT
1b1
Extended Addressing Support:
Indicates the number of address bits supported by the PE both as a
source and target of an operation.
3b001 indicates support for 34 bit addresses.
Extended Features:
PE has extended features list; the extended features pointer is valid.
COM_TRANS_SUP 1b0
Common Transport Large System Support:
When enabled it indicates support for 16 bit source and destination ID’s.
CRF_SUP
1b0
RE_TRNS_SUP
1b0
FLO_CNT_SUP
1b0
STD_RTCS
1b0
EXT_RTCS
1b0
MCAST_SUP
1b0
-
0
Critical Request Flow Support:
1b0 - PE does not support CRFS
1b1 - PE supports CRFS
SerB does not support CRFS, hence this bit is hard wired to zero.
Re-transmit Suppression Support:
1b0 - PE does not support RTSS
1b1 - PE supports RTSS
SerB does not support RTSS, hence this bit is hard wired to zero.
Flow Control Support:
SerB does not support FCS, hence this bit is hard wired to zero.
Standard route table configuration support:
SerB does not support SRTCS, hence this bit is hard wired to zero.
Extended route table configuration support:
SerB does not support ERTCS, hence this bit is hard wired to zero.
Multicast Extension Support:
SerB does not support Multicast, hence this bit is hard wired to zero.
Reserved.
DOORBELL
1b1
Indicates that the RIO controller supports inbound doorbells.
MAILBOX
4b0
Mailbox 3:0:
Bt 0 indicates PE supports inbound mailbox 0.
Bit 1 indicates PE supports inbound mailbox 1.
Bit 2 indicates PE supports inbound mailbox 2.
Bit 3 indicates PE supports inbound mailbox 3.
-
0
SWITCH
1b0
PROCESSOR
1b0
MEMORY
1b1
BRIDGE
1b0
Reserved.
Indicates that the PE can bridge to another external RIO interface.
Indicates that the PE physically contains a local processor that executes
code.
Indicates that the PE has physically addressable local address space and
can be accessed as an endpoint through non-maintenance operations.
Indicates that the PE can bridge to another interface.
Table 17 Process Element Features CAR
66 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.