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80KSBR200 Datasheet, PDF (10/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE
IDT 80KSBR200
Notes
1.1 Interface Overview
Advanced Datasheet*
sRIO 4 Tx lanes
1.25, 2.5 or 3.125Gbps
sRIO 4 Rx lanes
1.25, 2.5 or 3.125Gbps
P-Port Clock (4-pins)
.
.
P-Port Address (23 pins)
.
JTAG Interface (5 pins)
..
.
I2C Interface
.
400Khz F/S (13-pins)
.
.
Master Reset
REF_Clock (2 pins)
IDT80KSBR200
Serial Buffer
(SerB)
P-Port Rd/Wr Ctrl
P-Port D Bus (36 pins)
P-Port Q Bus (36 pins)
IRQ Output (2 pins)
R_Ext (External Resistance)
Figure 1 Diagram of SerB Interfaces
1.1.1 sRIO Port
The sRIO interface is the main communication port on the chip. This port is compliant with the serial RapidIOTM v. 1.3
specifications. Please refer to the serial RapidIOTM specifications for full detail.
There are 4 uni-directional differential links for a total of 8 pins. Each can run at 1.25, 2.5, or 3.125Gbps programmable.
Both sRIO data (sample) and maintenance packets are transmitted and received on these links.
1.1.2 Parallel Port
P-Port interface is used as a memory expansion port. As a memory expansion port, one of the designated QDR SRAM
devices can be connected. If P-Port is connected to one of the designated SRAM devices, it will maintain the clocking and
full interconnection to drive the SRAM device.
1.1.3 I2C Bus
This interface may be used as an alternative to the standard sRIO or JTAG ports to program the chip and to check the
status of registers - including the error reporting registers. It is fully compliant with the I2C specification, It has 13 pins and
supports both Fast- and Slow-mode buses [1]. Refer to the “I2C” chapter for full detail.
1.1.4 JTAG TAP Port
This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alterna-
tive to the standard sRIO or I2C ports to program the chip and to check the status of registers - including the error reporting
registers. It has 5 pins. Refer to the JTAG chapter for full detail.
10 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.