80KSBR200 Datasheet, PDF (88/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Name: P0_ERR_RATE_CSR Address: 0x00066C
Advanced Datasheet*
Bit
Field Name
15:0
23:16
-
ERR_DEG_TRIG
Reset
Value
0
0xFF
Comment
Reserved.
Error Rate Degraded Threshold Trigger:
These bits provide the threshold value for reporting an error condi-
tion due to a degrading link.
31:24 ERR_FAIL_TRIG 0xFF
0x00 - Disable the Error Rate Degraded Threshold Trigger
0x01 - Set the error reporting threshold to 1
0x02 - Set the error reporting threshold to 2
...
0xFF - Set the error reporting threshold to 255.
Error Rate Failed Threshold Trigger:
These bits provide the threshold value for reporting an error condi-
tion due to a possibly broken link:
Note:
1.
0x00 - Disable the Error Rate Failed Threshold Trigger
0x01 - Set the error reporting threshold to 1
0x02 - Set the error reporting threshold to 2
...
0xFF - Set the error reporting threshold to 255.
Table 50 Port 0 Error Rate Threshold CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.18
8.2 Configuration Registers
The configuration registers are grouped into functions with a maximum of 32 bits per register. Every configuration
register is assigned a reference number for ease of location. The reference number may be used as a pointer to the
address of the register whenever the configuration address is being loaded or read. The registers are read or programmed
as described in the programming section 6 of this datasheet. The registers are shown with bit 0 assigned as the LSB of the
register and bit 31 assigned as the MSB. Flag registers are 64 bits long with bit 63 assigned as the MSB.
Within the configuration registers there are five types of bits. The bit type is shown in the column labeled “type”. The five
types are:
HW Hard wired bits that are set by the hard wired configuration of the device. These cannot be changed by
any programming method and are not affected by any of the resets. These bits may be read by any of the
designated methods for reading configuration registers. These primarily deal with port structure and
electrical connections. The shadow is the external pin.
RST Bits that will enter a default mode based upon the hard-wired configuration during Master Reset.
Subsequently these bits may be changed by any of the designated programming methods, and then
performing a “load configuration” reset. These primarily deal with internal device structure. These
registers must have a shadow register. Whenever a register containing RST bits are read by any of the
designated reading methods, the actual content of the register is returned and not the content of the
shadow register.
RW Bits that may be changed at any time without a Load Configuration reset. In the event JTAG or I²C is
used to alter the content, a Load Configuration Reset must be performed. These primarily deal with data
routing and flagging. These registers have no shadow, except for the JTAG and I²C registers. These bits
may be read by any of the designated methods.
RO Read Only. Upon a master reset or load configuration, these will go to a known state, but once initialized
they are under control of the SerB internally. sRIO Transaction IDs are an example of a register that the
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
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