80KSBR200 Datasheet, PDF (89/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
interface must increment with each transaction, the user may read the register, but the user cannot
change the transaction IDs without causing a sequence error.
RC Read to Clear. These bits are associated with MBIST. Contained within the MBIST register is a bit to
indicate BIST is done. These bits will clear on read, only if MBIST is complete.
In addition, the configuration registers have a default mode. The defaults are shown in the column labeled “reset value”.
The reset values have the following form:
HW The bit is set by the hard-wired pin configuration during reset. Whether the user can subsequently
change or not depends upon the type. Protocols, port usage, etc. may affect the status of this bit.
0
Bit defaults to zero
1
Bit defaults to one
X
Bit must be programmed before use. The initial state is not a concern.
8.2.1 Reset and Command Register
This register may be written in order to perform a reset and other functions. The bits automatically clear after
performing the function, allowing the user to write again to perform an additional reset without having to clear the bits. The
use of any of these bits will clear the memory and reset all state machines. The bits are listed in priority, with Master Reset
overriding Partial Reset and Partial Reset overriding Load Configuration.
Name: RST_CMD_REG
Address: 0x18004
Bits Field Name
Type
Reset
Value
Comment
0
MR_RST
1
PR_RST
2
LD_CFG
RW
1b0
RW
1b0
RW
1b0
Master reset:
Hard Reset. The device will default to the hard wired configura-
tion
Partial Reset:
Loads the shadow into the configuration registers and resets
PLLs
Load Configuration:
Loads the shadow into the configuration registers
31:3 -
0
Reserved
Note:
1.
2.
3.
4.
Table 51 Reset and Command Register
See Section 6.3 for a complete description and functionality of these resets.
Partial reset must be used if the port configuration is changed.
Does not reset PLLs and cannot be used if the port configuration was changed.
There is a master reset used by sRIO described in the RapidIO Part 4: Physical Layer 8/16 LP VLDS Specifi-
cation.
8.2.2 Serial Port Configuration Register
The Serial Port Configuration Register sets the speed of S-Port. The serial port configuration register will default to
the configuration designated on the hard-wired inputs upon Master Reset. Once set, the register may be reconfigured as
described. At any time, full read access is available from all indicated ports.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.