80KSBR200 Datasheet, PDF (5/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
List of Tables
Table 1: SerB Memory Map
Table 2: Port-write Packet Data Payload for Error Reporting
Table 3: Physical RIO Errors Detected
Table 4: Physical RIO Threshold Response
Table 5: Hardware Errors for NRead Transaction
Table 6: Hardware Errors for Maintenance Read/Write Request Transaction
Table 7: Hardware Errors for RIO Write Class Transactions
Table 8: Hardware Errors for SWrite Class Transactions
Table 9: Hardware Errors for Maintenance Response Transactions
Table 10: Hardware Errors for Response Transactions
Table 11: Hardware Errors for Reserved FType
Table 12: RIO Base Feature Address Space
Table 13: Device ID CAR
Table 14: Device Information CAR
Table 15: Assembly ID CAR
Table 16: Assembly Info CAR
Table 17: Process Element Features CAR
Table 18: Source Operations CAR
Table 19: Destination Operations CAR
Table 20: Processing Element Logical Layer Control CSR
Table 21: Local Configuration Space Base Address 1 CSR
Table 22: Base Device ID CSR
Table 23: Host Base Device ID Lock CSR
Table 24: Component Tag CSR
Table 25: RIO Extended Features Address Space
Table 26: 1x/4x LP-Serial Register Block Header
Table 27: Port Link Time-out CSR
Table 28: Port Response Time-out CSR
Table 29: Port General Control CSR
Table 30: Port 0 Link Maintenance Request CSR
Table 31: Port 0 Link Maintenance Response CSR
Table 32: Port 0 Local ackID Status CSR
Table 33: Port 0 Error and Status CSR
Table 34: Port 0 Control CSR
Table 35: Error Management Extensions Block Header
Table 36: Logical/Transport Layer Error Detect CSR
Table 37: Logical/Transport Layer Error Enable CSR
Table 38: Logical/Transport Layer Address Capture CSR
Table 39: Logical/Transport Layer Device ID Capture CSR
Table 40: Logical/Transport Layer Control Capture CSR
Table 41: Port-write Target Device ID CSR
Table 42: Port 0 Error Detect CSR
Table 43: Port 0 Error Rate Enable CSR
Table 44: Port 0 Attribute Capture CSR
Table 45: Port 0 Packet/Control Symbol Capture 0 CSR
Table 46: Port 0 Packet/Control Symbol Capture 1 CSR
Table 47: Port 0 Packet/Control Symbol Capture 2 CSR
Table 48: Port 0 Packet/Control Symbol Capture 3 CSR
Table 49: Port 0 Error Rate CSR
Table 50: Port 0 Error Rate Threshold CSR
Table 51: Reset and Command Register
Table 52: Serial Port Configuration Register
Table 53: Parallel Port Configuration Register
Table 54: Memory Allocation Register
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.