80KSBR200 Datasheet, PDF (82/172 Pages) Integrated Device Technology – sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

IDT 80KSBR200
Notes
Advanced Datasheet*
Logical/Transport Layer Control Capture CSR
This register contains error information. LTLCCCSR is stored in each port and the Message Unit, although the values in
this register can differ between each port and Message Unit. The Message Unit LTLCCCSR cannot lock if any port has
locked; no port LTLCCCSR can lock if the Message Unit or any other port has locked. Undefined results will occur if this
register is written while actual Logical/Transport Layer errors are being detected by the port.
Name: LTL_CTRL_CAP_CSR Address: 0x00061C
Bit
Field Name
Reset
Value
Comment
15:0
23:16
-
MSG_INFO
0
0x00
27:24 TRANS_TYPE
0x0
31:28 FORMAT_TYPE
0x0
Reserved.
Message Information:
Letter, mbox, and message for the last Message request received for
the mailbox that had an error (Message errors only).
Transaction Type:
Transaction type associated with the error.
Format Type:
Format type associated with the error.
Note:
1.
Table 40 Logical/Transport Layer Control Capture CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.7
Port-write Target deviceID CSR
This register contains the target device ID to be used when a device generates a Maintenance port-write operation to
report errors to a system host.
Name: PORT_WR_TID_CSR Address: 0x000628
Bit
Field Name
Reset
Value
Comment
14:0
-
0
15
LRG_TRANS
1b0
23:16 DEV_ID
31:24 DEV_ID_MSB
0x00
0x00
Reserved.
Large Transport:
DeviceID size to use for a port-write
1b0 - use the small transport deviceID
1b1 - use the large transport deviceID.
DeviceID:
This is the port-write target deviceID.
DeviceID MSB:
This is the most significant byte of the port-write target deviceID
(large transport systems only).
Note:
1.
Table 41 Port-write Target deviceID CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.8
Port 0 Error Detect CSR
The Port 0 Error Detect Register indicates transmission errors that are detected by the hardware. Software can write
bits in this register with “1” to cause the Error Rate Counter to increment. Undefined results will occur if this register is
written while actual physical layer errors are being detected by the port.
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March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.