MB86296 Datasheet, PDF (86/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
In DDR (double data rate) DCLKO mode, two ouput phases can be identified both edge of DCLKO.
In SDR (sindle data rate) DCLKO mode, two output phases cab be identified an edge of HSYNC or
DE.
DCLKO(SDR)
HSYNC
Digital RGB
DE
ref edge
even clocks
sc0 is first
sc0 sc1
POM(parallel output mode) bit in DCM3 register definess which output mode is used, parallel or
multiplex.
CKddr( clock for double data rate) bit in DCM3 registerdefiness which DCLKO clock mode is used,
SDR or DDR.
The dual display function can not be used with external sync mode.
MB86296S<Coral-PA>
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Specification Manual Rev0.1