MB86296 Datasheet, PDF (325/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
14.4.3 Composite synchronous signal
When the EEQ bit of the DCM register is “0”, the CSYNC signal output waveform is as shown
below.
CSYNC
VSYNC
even field
odd field
CSYNC
VSYNC
odd field
even field
Fig 11.12 Composite Synchronous Signal without Equalizing Pulse
When the EEQ bit of the DCM register is “1”, the equalizing pulse is inserted into the CSYNC signal,
producing the waveform shown below.
CSYNC
VSYNC
CSYNC
VSYNC
even field
odd field
odd field
even field
Fig 11.13 Composite Synchronous Signal with Equalizing Pulse
The equalizing pulse is inserted when the vertical blanking time period starts. It is also inserted
three times after the vertical synchronization time period has elapsed.
MB86296S <Coral-PA>
315
Specification Manual Rev0.1