MB86296 Datasheet, PDF (191/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
GD (GPIO Data)
Register
address
HostBaseAddress + 00ACH
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name Reserved
GWE
Resv
GD
R/W
R0
W
R0
RW
Initial value
0
0
0
0 (*1)
*1 – initial value will be affected by state of GPIO pins
This register contains the GPIO read/write data field and the write mask when setting GPIO outputs.
Bit 13 to
Bit 0
Bit 24 to
Bit 16
GD (GPIO Data)
This field is used for both reading the value of GPIO inputs and specifying the value for
GPIO outputs. When writing to this field only those pins with the corresponding bit set in the
GWE field will be changed. The bit positions refer to the following pins:
Bit 0: EDO
Bit 1: EDI
Bit 2: ECK
Bit 3: ECS
Bit 4: EE
Bit 5: BC
Bit 6: TC
Bit 7: SB
Bit 8: BEN
Bit 9: GI0
Bit 10: GI1
Bit 11: GI2
Bit 12: GI3
Bit 13: GI4
GWE (GPIO Write Enable)
When writing values to the GPIO Outputs using the GD field, this field specifies those bits
which are being written to. If a bit in this field is “1b” then the corresponding bit will be
written to. Otherwise if a bit it “0b” the corresponding bit will remain unchanged. The bit
positions refer to the following pins:
Bit 16: EDO
Bit 17 EDI
Bit 18: ECK
Bit 19: ECS
Bit 20: EE
Bit 21: BC
Bit 22: TC
Bit 23: SB
Bit 24: BEN
MB86296S <Coral-PA>
181
Specification Manual Rev0.1