MB86296 Datasheet, PDF (84/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
7.8DCLKO shift
1) Delay
DCLKO delay function is available if internal PLL is used for DCLK. CKDe-bit of DCM3 enables this
function. Delay number is specified at CKDn-field of DCM3 register.
CKDn delay
00000 t
00001 1.5t
00010 2t
:
:
11110 16t
11111 16.5t
t= one cycle of internal PLL or 2.5ns (400MHz osc).
2) Inversion
DCLKO inversion is also available with/without delay function. This function is effective with no
relation to DCLK clock source.
CKinv-bit of DCM3 enables this function.
7.9Synchronous register update of display
To update position related parameters without disturbing display, it is need to update synchronously
with VSYNC interrupt and finish at a time.
This synchronous register update mode eases this limitation. In this mode, written parameters are hold
in intermediate registers and update at once synchronously with VSYNC.
RUM- bit of DCM3 register enables this mode.
RUF-bit of DCM3 register controls start of update and shows whether update is done or not.
MB86296S<Coral-PA>
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Specification Manual Rev0.1