MB86296 Datasheet, PDF (320/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
14.3.4 Timing of write access to different row addresses
MCLKO
TRAS
MRAS
MCAS
MWE
MA
TRCD
ROW
COL
TRP
TRCD
ROW
COL
MD
DATA
DATA
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
TRAS: RAS Active Time
TRCD: RAS to CAS Delay Time
TRP: RAS Precharge Time
Fig. 11.6 Timing of Write Access to Different Row Addresses
The above timing diagram shows that write access is made from CORAL to different row
addresses of SDRAM. The first and next address to be write fall across an SDRAM page boundary,
so the Pre-charge command is issued at the timing satisfying TRAS, and then after the elapse of
TRP, the ACTV command is reissued, and then the WRITE command is issued.
MB86296S<Coral-PA>
310
Specification Manual Rev0.1