MB86296 Datasheet, PDF (189/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
SRBS (Slave Read Burst Size)
Register
address
HostBaseAddress + 00A4H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
SRBS
R/W
R0
RW
Initial value
0
0
This register specifies the length of a burst read through the PCI Slave Interface as SRBS+1. By
default this register is set to “000b” indicating a burst read length of 1 dword. The maximum setting is
7 (“111b”) and indicates a burst read length of 8 dwords.
IOM (IO Mode)
Register
address
HostBaseAddress + 00A8H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Resv.
GIM
GD
R/W
R0
RW
RW
Initial value 0
0
0
0 *1 0 0 0 0 *2
*1 – initial reset value specified by Burst Enable pin state at reset.
*2 – initial reset value specified by Transfer Complete pin state at reset.
This register determines the function of those Coral PA pins under the control of the host interface.
It also defines the direction (input/output) of any GPIO.
Bit 0 EEE (EEPROM Enable)
If set then the PCI EEPROM Configuration function is enabled. This field takes it’s reset
value from the Transfer Complete pin at system reset. Note that if the RGB input is enabled
then the EEPROM interface us disabled regardless of the value of this register. If this field
is “0b” (and the RGB input is not enabled) then the EEPROM pins operate either as serial
interface pins or GPIO as determined by the SER field.
Bit 1 BCE (Burst Complete Enable)
If set to “1b” then the BC pin operates as Burst Complete. Otherwise if set to “0b” it
operates as a GPIO. If the RGB input is enabled this field is ignored and the BC pin
operates as an RGB input pin.
Bit 2 TCE (Transfer Complete Enable)
If set to “1b” then the TC pin operates as Transfer Complete. Otherwise if set to “0b” it
operates as GPIO.
Bit 3 SBE (Slave Busy Enable)
If set to “1b” then the SB pin operates as Slave Busy. Otherwise if set to “0b” it operates as
a GPIO. If the RGB input is enabled this field is ignored and the SB pin operates as an
RGB input pin.
Bit 4 BEE (Burst Enable Enable)
If set to “1b” then the BEN pin operates as Burst Enable. Otherwise if set to “0b” it operates
as GPIO.
Bit 5 RGB (RGB input enable)
If set to “1b” then the RGB input is enabled. This field takes its reset value from the Burst
Enable pin at system reset and overrides all other IO enable fields.
MB86296S <Coral-PA>
179
Specification Manual Rev0.1