MB86296 Datasheet, PDF (55/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
5.2.2 Block Function Overview
START condition / STOP condition detecting circuit
This circuit performs detection of START condition and STOP condition from the state of SDA
and SCL.
START condition / STOP condition generating circuit
This circuit performs generation of START condition and STOP condition by changing the state of
SDA and SCL.
Arbitration Lost detecting circuit
This circuit compares the data output to SDA line with the data input into SDA line at the time of
data transmission, and it checks whether these data is in agreement. When not in agreement, it
generates arbitration lost.
Shift Clock generating circuit
This circuit performs generating timing count of the clock for serial data transfer, and output
control of SCL clock by setup of a clock control register.
Comparater
Comparater compares whether the received address and the self-address appointed to be the
address register is in agreement, and whether the received address is a global address.
ADR
ADR is the 7-bit register which appoints a slave address.
DAR
DAR is the 8-bit register used by serial data transfer.
BSR
BSR is the 8-bit register for the state of I2C bus etc. This register has following functions:
- detection of repeated START condition
- detection of arbitration lost
- storage of acknowledge bit
- data transfer direction
- detection of addressing
- detection of general call address
- detection of the 1st byte
BCR
BCR is the 8-bit register which performs control and interruption of I2C bus. This register has
following functions:
- request / permission of interruption
- generation of START condition
- selection of master / slave
- permission to generate acknowledge
MB86296S <Coral-PA>
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Specification Manual Rev0.1