MB86296 Datasheet, PDF (196/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
BSA (Burst Source Address)
Register
address
HostBaseAddress + 8000H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
SA
R/W
RW
Initial value
0
This register specifies the initial source address for a transfer controlled by the Burst Control Unit.
Its interpretation (internal Coral/external PCI) will depend on the transfer mode specified in the BSR
register.
BDA (Burst Destination Address)
Register
address
HostBaseAddress + 8004H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
DA
R/W
RW
Initial value
0
This register specifies the initial destination address for a transfer controlled by the Burst Control
Unit. Its interpretation (internal Coral/external PCI) will depend on the transfer mode specified in the
BSR register.
BCR (Burst Control Register)
Register
address
HostBaseAddress + 8008H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
*1 BSIZE
TSIZE
R/W
RW
RW
Initial value 0 0 0 0 0
0
*1 - Reserved
This register specifies the length and address manipulation performed for a transfer. It can also be
used to start a transfer.
Bit 23 to 0 TSIZE
This field specifies the overall transfer length as a number of dwords. A transfer will be
split up into a number of bursts whose length is specified by the BSIZE field.
Bit 27 to 24 BSIZE (Burst Size)
This field specifies the length of a BCU controlled burst as a number of dwords. One or
more bursts will make up an overall transfer. Note that if TSIZE is not an exact multiple of
BSIZE the final burst of a transfer will be less than BSIZE.
Bit 29
NSA (New Source Address)
If this bit is set to “1b” then after each burst the source address is incremented by the
burst size. This means that a large continuous section of memory can be transferred. If
this bit is “0b” then successive bursts will always be from the initial specified start
address. This mode could be used if transferring data from a FIFO like interface.
Bit 30
NDA (New Destination Address)
If this bit is set to “1b” then after each burst the destination address is incremented by the
burst size. This means that data can be transferred into a large continuous section of
memory. If this bit is “0b” then successive bursts will always be to the initial specified
destination address. This mode should be used when transferring data to the FIFO.
MB86296S<Coral-PA>
186
Specification Manual Rev0.1