MB86296 Datasheet, PDF (202/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
1: Permission of interrupt
Bit0
INT (INTrrupt)
Flag bit for request of interruption for transfer end
When this bit is “1” SCL line is maintained at “L” level. If this bit is cleared by being
written “0”, SCL line is released and the following byte transfer is started. Moreover, it is
reset to “0” by generating of START condition or STOP condition at the time of a master.
write case
0: The flag is cleared.
1: Don’t care.
read case
0: The transfer is not ended.
1: It is set when 1 byte transfer including the acknowledge bit is completed and it
corresponds to the following conditions.
- It is a bus master.
- It is an addressed slave.
- It was going to generate START condition while other systems by which arbitration lost
happened used the bus.
Competition of SCC, MSS and INT bit
Competition of the following byte transfer, generation of START condition and generation of STOP
condition happens by the simultaneous writing of SCC, MSS and INT bit. The priority at this case is as
follows.
1) The following byte transfer and generation of STOP condition
If “0” is written to INT bit and “0” is written to MSS bit, priority will be given to “0” writing to MSS bit
and STOP condition will be generated.
2) The following byte transfer and generation of START condition
If “0” is written to INT bit and “1” is written to SCC bit, priority will be given to “1” writing to SCC bit
and START condition will be generated.
3) Generation of START condition and STOP condition
The simultaneous writing of “1” to SCC bit and “0” to MSS bit is prohibition.
MB86296S<Coral-PA>
192
Specification Manual Rev0.1