MB86296 Datasheet, PDF (203/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
CCR (Clock Control Register)
Register
address
I2C Base Address + 0008h
Bit No
7
6
5
4
3
2
1
0
Bit field name -
HSM
EN
CS4
CS3
CS2
CS1
CS0
R/W
R1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
0
-
-
-
-
-
Bit7
Nonuse
“1” is always read at read.
Bit6
HSM (High Speed Mode)
Select
standard-mode
/
high-speed-mode
0:
Standard-mode
1: High-speed-mode
Bit5
EN (Enable)
Permission of operation
When this bit is “0”, each bit of BSR and BCR register (except BER and BEIE bit) is
cleared. This bit is cleared when BER bit is set.
0: Prohibition of operation
1: Permission of operation
Bit4
CS4 - 0 (Clock Period Select4 - 0)
Set up the frequency of a serial transfer clock
Frequency fscl of a serial transfer clock is shown as the following formula.
Please set up fscl not to exceed the value shown below at the time of master operation.
standard-mode: 100KHz
high-speed-mode: 400KHz
standard-mode
fscl = A
(2 x m)+2
high-speed-mode
fscl = A
int(1.5 x m)+2
A: I2C system clock = 16.6MHz
<Notes>
+2 cycles are minimum overhead to confirm that the output level of SCL terminal changed. When the
delay of the positive edge of SCL terminal is large or when the clock is extended by the slave device, it
becomes larger than this value.
The value of m becomes like the following page to the value of CS 4-0.
MB86296S <Coral-PA>
193
Specification Manual Rev0.1