MB86296 Datasheet, PDF (274/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
CDCN (Capture Data Count for NTSC)
Register
address
CaputureBaseAddress + 4000h
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
field
name
Reserve
d
BDCN
Reserve
d
VDCN
R/W
RX
RW
RX
RW
Initial value X
0x10f(271)
X
0x5A3(1443)
This register sets the count of data of the input video stream in NTSC format.
Bit12-0
Bit28-16
VDCN (Valid Data Count for NTSC)
Sets count of data processed during valid period in NTSC format. The setting value +1 is a
data number
BDCN (Blanking Data Count for NTSC)
Sets count of data processed during blanking period in NTSC format. The setting value +1 is
a data number
4T
4T
4T
VI[7:0]
EAV ^{Blanking data} SAV
80,10,80,10,80,.
H-BLANK
276T 525
288T 625
272T(BDCN:271T)
284T(BDCP:283T)
Multiplexed video data _EAV
C b,Y,Cr,Y,C b,Y,C r,Y,… ..
ACTIVE-VIDEO
1440T [525]
1440T [625]
1444T(VDCN:1443T)
1444T(VDCP:1443T)
The range of VDCN and BDCN is shown in the following figure.
SAV: start of active video timing reference code
EAV: end of active video timing reference code
T: clock period 37 ns nom.
MB86296S<Coral-PA>
264
Specification Manual Rev0.1