MB86296 Datasheet, PDF (187/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
SRST (Software ReSeT)
Register
address
HostBaseAddress + 2CH
Bit number 7
6
5
4
3
2
1
0
Bit field name
Reserved
SRST
R/W
R0
W1
Initial value
0
0
This register controls software reset. When “1” is set to this register, a software reset is performed.
CCF (Change of Clock Frequency)
Register
address
HostBaseAddress + 0038H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
CGE COT
Reserved
R/W
RW0
RW RW
RW0
Initial value
0
00 00
0
This register changes the operating frequency.
Bit 19 and 18
CGE (Clock select for Geometry Engine)
Selects the clock for the geometry engine
11 Reserved
10 166 MHz
01 133 MHz
00 100 MHz
Bit 17 and 16
COT (Clock select for the others except-geometry engine)
Selects the clock for other than the geometry engine
11 Reserved
10 Reserved
01 133 MHz
00 100 MHz
Notes:
1. Write “0” to the bit field other than the above ([31:20], [15:00]).
2. Operation is not assured when the clock setting relationship is CGE < COT.
MB86296S <Coral-PA>
177
Specification Manual Rev0.1