MB86296 Datasheet, PDF (323/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
14.4 Display Timing
14.4.1 Non-interlace mode
Ri/Gi/Bi
HSYNC
VSYNC
VTR+1 rasters
VSP+1 rasters
VDP+1 rasters
VSW+1 rasters
Assert Frame Interrupt
Assert Vsync Interrupt
Ri/Gi/Bi
DISPE
HSYNC
Latency 13 clocks
HDP+1 clocks
HSP+1 clocks
HTP+1 clocks
HSW+1 clocks
DCLKO
Ri/Gi/Bi
DISPE
012
n−2 n−1
n=HDP+1
Fig. 11.10 Non-interlace Timing
In the above diagram, VTR, HDP, etc., are the setting values of their associated registers.
The VSYNC/frame interrupt is asserted when display of the last raster ends. When updating
display parameters, synchronize with the frame interrupt so no display disturbance occurs.
Calculation for the next frame is started immediately after the vertical synchronization pulse is
asserted, so the parameters must be updated by the time that calculation is started.
VSYNC is output 1 dot clock faster than HSYNC.
MB86296S <Coral-PA>
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Specification Manual Rev0.1