MB86296 Datasheet, PDF (64/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
5.5 Note
A ) About a 10-bit slave address
This module does not support the 10-bit slave address. Therefore, please do not specify the slave
address of from 78H to 7bH to this module. If it is specified by mistake, a normal transfer cannot be
performed although acknowledge bit is returned at the time of 1 byte reception.
B ) About competition of SCC, MSS, and INT bit
Competition of the following byte transfer, generation of START condition, and generation of STOP
condition happens by the simultaneous writing of SCC, MSS, and INT bit. At this time the priority is
as follows.
1) The following byte transfer and generation of STOP condition
If “0” is written to INT bit and “0” is written to MSS bit, priority will be given to “0” writing to MSS
bit and STOP condition will be generated.
2) The following byte transfer and generation of START condition
If “0” is written to INT bit and “1” is written to SCC bit, priority will be given to “1” writing to SCC
bit and START condition will be generated.
3) Generation of START condition and generation of STOP condition
The simultaneous writing of “1” in SCC bit and “0” to MSS bit is prohibition.
C ) About setup of S serial transfer clock
When the delay of the positive edge of SCL terminal is large or when the clock is extended by the
slave device, it may become smaller than setting value (calculation value) because of generation of
overhead.
MB86296S<Coral-PA>
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Specification Manual Rev0.1