MB86296 Datasheet, PDF (328/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
15.3.2 Note at power-on
• There is no restriction on the sequence of power-on/power-off between V_DDL and V_DDH. However, do
not apply only V_DDH for more than a few seconds.
• Do not input HSYNC, VSYNC, and EO signals when the power supply voltage is not applied. (See
the input voltage item in Maximum rating.)
• There reset sequences is as follows:
S is changed from “Low” to “High” levels and then XRST is changed from “Low” to “High” level:
VDDL
VDDH
PCLK
More than 10clk
More than 10clk
S
XRST
More than 500ns
300µs
Immediately after power-on, input the “Low” level to the S and XRST pins for 500 ns or more. After
the S pin is set to “High” level, input the “Low” level to the XRST pins for 300 µs or more
continuously.
The S and XRST pins are reset during “Low” level period.
Immediately after power-on, input clock to the PCLK pin for 10 clk or more. The XRST is taken in
synchronizing with the PCLK.
MB86296S<Coral-PA>
318
Specification Manual Rev0.1