MB86296 Datasheet, PDF (57/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
5.4 Function overview
Two bi-directional buses, serial data line (SDA) and serial clock line (SCL), carry information at I2C-
bus. Scarlet I2C interface has SDA input (SDAI) and SDA output (SDAO) for SDA and is connected to
SDA line via open-drain I/O cell. And this interface also has SCL input (SCLI) and SCL output (SCLO)
for SCL line and is connected to SCL line via open-drain I/O cell. The wired theory is used when the
interface is connected to SDA line and SCL line.
5.4.1 START condition
If “1” is written to MSS bit while the bus is free, this module will become a master mode and will
generate START condition simultaneously. In a master mode, even if a bus is in a use state (BB=1),
START condition can be generated again by writing “1” to SCC bit.
There are two conditions to generate START condition.
- “1” writing to MSS bit in the state where the bus is not used (MSS=0 & BB=0 & INT=0 & AL=0)
- “1” writing to SCC bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0)
If “1” writing is performed to MSS bit in an idol state, AL bit will be set to “1”. “1” writing to MSS bit
other than the above is disregarded.
SDA
SCL
START condition
5.4.2 STOP condition
If “0” is written to MSS bit in a master mode (MSS=1), this module will generate STOP condition and
will become a slave mode.
There is a condition to generate STOP condition.
- “0” writing to MSS bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0)
“0” writing to MSS bit other than the above is disregarded.
SDA
SCL
STOP condition
MB86296S <Coral-PA>
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Specification Manual Rev0.1