MB86296 Datasheet, PDF (254/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
L3ETC (L3 layer Extend Transparency Control)
Register
address
DisplayBaseAddress + 1ACH
Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name L3ETZ Reserved
L3TEC
R/W RW R0
RW
Initial value 0
0
This register sets the transparent color for the L3 layer. The 24 bits/pixel transparent color is set
using this register. The lower 15 bits of this register are physically the same as L3TC. Also, L3ETZ
is physically the same as L3TZ.
When L3ETC = 0 and L3EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0 L3ETC (L3 layer Extend Transparent Color)
Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to
0 are used.
Bit 31
L3EZT (L3 layer Extend Zero Transparency)
Sets handling of color code 0 in L3 layer
0 Code 0 as transparency color
1 Code 0 as non-transparency color
L4ETC (L4 layer Extend Transparency Control)
Register
address
DisplayBaseAddress + 1B0H
Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name L4ETZ Reserved
L4TEC
R/W RW R0
RW
Initial value 0
0
This register sets the transparent color for the L4 layer. This register sets the transparent color for
the L4 layer. When L4ETC = 0 and L4EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0 L4ETC (L4 layer Extend Transparent Color)
Sets transparent color code for the L4 layer. In indirect color mode (8 bits/pixel) bits 7 to
0 are used.
Bit 31
L4EZT (L4 layer Extend Zero Transparency)
Sets handling of color code 0 in L4 layer
0 Code 0 as transparency color
1 Code 0 as non-transparency color
MB86296S<Coral-PA>
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Specification Manual Rev0.1