MB86296 Datasheet, PDF (252/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
L3TC (L3 layer Transparency Control)
Register
address
DisplayBaseAddress + C0H
Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name L3ZT
L3TC
R/W RW
RW
Initial value 0
Don’t care
This register sets the transparent color for the L3 layer. When L3TC = 0 and L3ZT = 0, color 0 is
displayed in black (transparent).
This register corresponds to the MLTC register for previous products.
Bit 14 to 0 L3TC (L3 layer Transparent Color)
Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to
0 are used.
Bit 15
L3ZT (L3 layer Zero Transparency)
Sets handling of color code 0 in L3 layer
0 Code 0 as transparency color
1 Code 0 as non-transparency color
L0ETC (L0 layer Extend Transparency Control)
Register
address
DisplayBaseAddress + 1A0H
Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name L0ETZ Reserved
L0TEC
R/W RW R0
RW
Initial value 0
0
This register sets the transparent color for the L0 layer. The 24 bits/pixel transparent color is set
using this register. The lower 15 bits of this register are physically the same as L0TC. Also, L0ETZ
is physically the same as L0TZ.
When L0ETC = 0 and L0EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0 L0ETC (L0 layer Extend Transparent Color)
Sets transparent color code for the L0 layer. In indirect color mode (8 bits/pixel) bits 7 to
0 are used.
Bit 31
L0EZT (L0 layer Extend Zero Transparency)
Sets handling of color code 0 in L0 layer
0 Code 0 as transparency color
1 Code 0 as non-transparency color
MB86296S<Coral-PA>
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Specification Manual Rev0.1