MB86296 Datasheet, PDF (240/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
CUTC (Cursor Transparent Control)
Register
address
DisplayBaseAddress + A0H
Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
CUZT
CUTC
R/W
R0
RW
RW
Initial value
0
Don’t
care
Don’t care
Bit 7 to 0 CUTC (Cursor Transparent Code)
Sets color code handled as transparent code
Bit 8
CUZT (Cursor Zero Transparency)
Defines handling of color code 0
0 Code 0 as non-transparency color
1 Code 0 as transparency color
CPM (Cursor Priority Mode)
Register
address
DisplayBaseAddress + A2H
Bit number 7
6
5
4
Bit field name
Reserved
CEN1 CEN0
R/W
R0
RW
RW
Initial value
0
0
0
3
2
Reserved
R0
0
1
CUO1
RW
0
0
CUO0
RW
0
This register controls the display priority of cursors. Cursor 0 is always preferred to cursor 1.
Bit 0
CUO0 (Cursor Overlap 0)
Sets display priority between cursor 0 and pixels of Console layer
0 Puts cursor 0 atlower than L0 layer.
1 Puts cursor 0 athigher than L0 layer.
Bit 1
CUO1 (Cursor Overlap 1)
Sets display priority between cursor 1 and C layer
0 Puts cursor 1 atlo wer than L0 layer.
1 Puts cursor 1 atlower than L0 layer.
Bit 4
CEN0 (Cursor Enable 0)
Sets enabling display of cursor 0
0 Disabled
1 Enabled
Bit 5
CEN1 (Cursor Enable 1)
Sets enabling display of cursor 1
0 Disabled
1 Enabled
MB86296S<Coral-PA>
230
Specification Manual Rev0.1