MB86296 Datasheet, PDF (46/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
4. HOST INTERFACE
The Coral PA has a 33MHz, 32-bit PCI host interface compliant to PCI version 2.1. It includes both
PCI master and PCI slave functions and an internal DMA/burst controller for multi-burst transfers of
large quantities of data between all combinations of PCI data space and Coral PA internal data space.
PCI EEPROM configuration is also supported.
Additional functions provided by the host interface are optional host interface status/control signals
which may aid in the reduction of PCI retries, the provision of general purpose IO (GPIO) signals for
control of external devices via the PCI interface including support for a simple serial interface.
4.1 Standard PCI Slave Accesses
An external PCI master will access the Coral PA as a PCI slave.
4.1.1 PCI Slave Write
For a PCI slave write, data will be “posted” into a temporary buffer from where it is written to the target
internal client. This temporary buffer is 8 dwords deep. PCI slave writes of any size are supported but
typically a retry will occur after each 8 dword burst. Note that when writing to the display list FIFO a
burst should be no more than 16 dwords (64 bytes) due to FIFO address space limitations.
When the write from the temporary buffer to the internal client is being performed the Slave Busy (SB)
signal becomes active. While this is happening PCI accesses will be rejected. If the SB signal is used
then PCI retries may be reduced.
4.1.2 PCI Slave Read
For a PCI slave read the read requested will be passed to an internal client from where data will be
fetched into the temporary buffer (8 dwords deep). Typically a retry will occur to actually fetch the data.
In order to fetch the correct number of words from the read address the burst size must be specified.
This is done by writing to the Slave Burst Read Size (SRBS) register. Bursts of between 1 and 8
dwords are supported. If the PCI master retries and reads less than the specified burst size then the
remaining dwords will be discarded. This means that the Slave Burst Read Size can be permanently
configured as 8 dwords. However there will be an increased latency on the pre-fetch stage if this is
done.
When data is transmitted in large quantities from a graphics memory, Please set 0x00000000 to
TRC(HostBase+00b8h) before using this function. The pre-fetch function is turned ON and improves
transfer rate. Please set the pre-fetch function as OFF according to the procedure of the explanation
part of a TRC register after slave burst READ to the last graphic memory.
4.2 Burst Controller Accesses (including PCI Master)
The Coral PA host interface includes a burst controller which can be used for transferring large
quantities of contiguous data between all combinations (source/destination) of PCI data space and
Coral PA internal data space. Control/status monitoring is done through internal registers with the
optional aid of external signals – Burst Complete (BC), Transfer Complete (TC) and Burst Enable
(BEN).
MB86296S<Coral-PA>
36
Specification Manual Rev0.1