MB86296 Datasheet, PDF (318/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
14.3.2 Timing of read access to different row addresses
MCLKO
TRAS
TRP
MRAS
TRCD
TRCD
MCAS
MWE
MA
ROW
COL
ROW
CL
MD
DATA
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
TRAS: RAS Active Time
TRCD: RAS to CAS Delay Time
CL: CAS Latency
TRP: RAS Precharge Time
COL
CL
DATA
*Timing when CL2 operating
Fig. 11.4 Timing of Read Access to Different Row Addresses
The above timing diagram shows that read access is made from CORAL to different row addresses
of SDRAM. The first and next address to be read fall across an SDRAM page boundary, so the
Pre-charge command is issued at the timing satisfying TRAS, and then after the elapse of TRP,
the ACTV command is reissued, and then the READ command is issued.
MB86296S<Coral-PA>
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Specification Manual Rev0.1