MB86296 Datasheet, PDF (291/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
TIS (Tile Size)
Register
address
DrawBaseAddress + 468H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
TISN
TISM
R/W
RW
RW
Initial value
1000000
1000000
This register specifies the tile size (m, n).
Bit 6 to 0 TISM (Title Size M)
Sets horizontal tile size. Any power of 2 between 4 and 64 can be used. Values that are
not a power of 2 cannot be used.
0.000100 M=4
0001000 M=8
0010000 M=16
0100000 M=32
1000000 M=64
Other than Setting disabled
the above
Bit 22 to 16
TISN (Title Size N)
Sets vertical tile size. Any power of 2 between 4 and 64 can be used. Values that are
not a power of 2 cannot be used.
0000100 N=4
0001000 N=8
0010000 N=16
0100000 N=32
1000000 N=64
Other than Setting disabled
the above
TOA (Texture Buffer Offset address)
Register
address
DrawBaseAddress + 46CH
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
XBO
R/W
RW
Initial value
Don’t care
This register sets the texture buffer offset address. Using this offset value, texture patterns can be
referred to the texture buffer memory.
Specify the word-aligned byte address (16 bits). (Bit 0 is always “0”.)
MB86296S <Coral-PA>
281
Specification Manual Rev0.1