MB86296 Datasheet, PDF (197/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
Bit 31
STRT (STaRT transfer)
When set to “1b” a transfer is started. Otherwise the transfer will wait until triggered wither
through the Burst Enable Register (BER) or via the external burst enable signal.
BSR (Burst Setup Register)
Register
address
HostBaseAddress + 800CH
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
MODE
R/W
R0
RW
Initial value
0
00000 0
This register specifies the type of a transfer (interpretation of the addresses) and specifies the
setup of control signals/status bits.
Bit 2 to 0
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
MODE (transfer MODE)
This field specifies the mode of the transfer and thus the interpretation of the
source/destination addresses.
000b: Slave Mode PCI to Coral
001b: Slave Mode Coral to PCI
010b: Coral to Coral (internal transfer)
011b: Reserved
100b: PCI to Coral (PCI Master read)
101b: Coral to PCI (PCI Master write)
110b: PCI to PCI (PCI Master read/write external DMA transfer)
111b: Reserved
Refer to Chapter 3 for a detailed explanation of these modes.
EXTEN (EXTernal ENable)
If set to “1b” then the external BEN (Burst Enable) signal may be used to initiate and
pause a transfer. Otherwise if set to “0b” the external BEN signal is ignored.
BCM (Burst Complete Mask)
If set to “1b” then the external BC signal will be active. Otherwise if set to “0b” it will
remain inactive low. Note that this bit does not affect the Burst Complete indication in the
main interrupt status register (IST) or the triggering of the main external interrupt.
TCM (Transfer Complete Mask)
If set to “1b” then the external TC signal will be active. Otherwise if set to “0b” it will
remain inactive low. Note that this bit does not affect the Transfer Complete indication in
the main interrupt status register (IST) or the triggering of the main external interrupt.
IMODE (Interrupt Mode)
This bit controls how the external BC/TC signals operate. If set to “0b” they are active
high. Otherwise if set to “1b” they toggle at each change of state removing the need for
the host to read/write the status register to clear them down.
Note that when using the Burst Complete/Transfer Complete indications via the main
interrupt status register this field should always be “0b”.
XCOR (not Clear On Read)
If set to “0b” then the Burst Complete/Transfer Complete fields in the Burst Status register
are clear on read. Otherwise if set to “1b” they must be manually written.
MB86296S <Coral-PA>
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Specification Manual Rev0.1