MB86296 Datasheet, PDF (43/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
2.3.6 Clock input
Table 2-4 Clock Input Pins
Pin name
CLK
S
CKM
CSL [1:0]
I/O
Input
Input
Input
Input
Description
Clock input signal
PLL reset signal
Clock mode signal
Clock rate select signal
Inputs source clock for internal operation clock and display dot clock. Normally, 4 Fsc (= 14.31818
MHz: NTSC) is input. An internal PLL generates the internal operation clock of 166 MHz/133 MHz
and the display base clock of 400 MHz. Even if don’t use an internal PLL (use BCLKI as internal clock
and use DCLKI as dot clock), don’t stop the PLL (Not fixed the S pin to low level).
CKM
L
H
Clock mode
Output from internal PLL selected
PCI bus clock selected
• When CKM = L, selects input clock frequency when built-in PLL used according to setting of CSL
pins
CSL1
L
L
H
H
CSL0
L
H
L
H
Input clock
frequency
Inputs 13.5-MHz
clock frequency
Inputs 14.32-MHz
clock frequency
Inputs 17.73-MHz
clock frequency
Inputs 33.33-MHz
clock frequency
Multiplication
rate
× 29
× 28
× 22
× 12
Display
reference clock
391.5 MHz
400.96 MHz
390.06 MHz
399.96
Please connect the crystal oscillator directly with the terminal CLK.
MB86296S <Coral-PA>
33
Specification Manual Rev0.1