MB86296 Datasheet, PDF (186/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
IMASK (Interrupt MASK)
Register
address
HostBaseAddress + 24H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
IMASK
*1
Reserved
Resv
Reserved
Reserve
d
IMASK
IMASK
R/W
RW R0
R0
R0
RW RW
Initial value
0
0
0
0
0
0
0
0
*1 Reserved
This register masks interrupt requests. Even when the interrupt request is issued for the bit to
which “0” is written, interrupt signal is not asserted for CPU.
Bit 0 CERRM (Command Error Interrupt Mask)
Masks drawing command execution error interrupt
Bit 1 CENDM (Command Interrupt Mask)
Masks drawing command end interrupt
Bit 2 VSYNCM (Vertical Sync. Interrupt Mask)
Masks vertical synchronization interrupt
Bit 3 FSYNCH (Frame Sync. Interrupt Mask)
Masks frame synchronization interrupt
Bit 4 SYNCERRM (Sync Error Mask)
Masks external synchronization error interrupt
Bit 5 REGUD (Register update)
Masks register update interrupt
Bit 26 SIIM (Serial Interface Interrupt)
Masks serial interface interrupt.
Bit 27 GIM (GPIO Interrupt)
Masks GPIO interrupt.
Bit 28 BCM (Burst Complete)
Masks Burst Complete interrupt.
Bit 29 TCM (Transfer Complete)
Masks Transfer complete interrupt.
Bit 30 HFM (HIF Fatal)
Masks HIF fatal interrupt.
Bit 31 ^{AEM (Address Error)}
Masks address error interrupt.
MB86296S<Coral-PA>
176
Specification Manual Rev0.1