MB86296 Datasheet, PDF (58/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
5.4.3 Addressing
In a master mode, it is set to BB=”1” and TRX=”0” after generation of START condition, and the
contents of DAR register are output from MSB. When this module receives acknowledge after
transmission of address data, the bit-0 of transmitting data (bit-0 of DRA register after transmission) is
reversed and it is stored in TRX bit.
- Transfer format of slave address
A transfer format of slave address is shown below:
MSB
LSB
A6 A5 A4 A3 A2 A1 A0 R/W ACK
slave address
- Map of slave address
A map of slave address is shown below:
slave address
0000 000
0000 000
0000 001
0000 010
0000 011
0 0 0 0 1XX
0 0 0 1 XXX
1 1 1 0 XXX
1 1 1 1 0 XX
1 1 1 1 1 XX
R/W Description
0
General call address
1
START byte
X
CBUS address
X
Reserved
X
Reserved
X
Reserved
X
Available slave address
X
10-bit slave addressing*1
X
Reserved
*1 This module does not support 10-bit slave address.
5.4.4 Synchronization of SCL
When two or more I2C devices turn into a master device almost simultaneously and drive SCL line,
each devices senses the state of SCL line and adjusts the drive timing of SCL line automatically in
accordance with the timing of the latest device.
MB86296S<Coral-PA>
48
Specification Manual Rev0.1