MB86296 Datasheet, PDF (321/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
14.3.5 Timing of read/write access to same row address
MCLKO
MRAS
TRCD
MCAS
MWE
MA
ROW
MD
COL
COL
CL
LOWD
DATA
DATA
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
TRAS: RAS Active Time
TRCD: RAS to CAS Delay Time
CL: CAS Latency
TRP: RAS Precharge Time
LOWD: Last Output to Write Command Delay
Timing when CL2 operating
Fig. 11.7 Timing of Read/Write Access to Same Row Address
The above timing diagram shows that write access is made immediately after read access is made
from CORAL to the same row address of SDRAM.
Read data is output from SDRAM, LOWD elapses, and then the WRITE command is issued.
MB86296S <Coral-PA>
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Specification Manual Rev0.1