MB86296 Datasheet, PDF (205/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
Address Register(ADR)
Register
address
I2C Base Address + 000Ch
Bit No
7
6
5
4
3
2
1
0
Bit field name -
A6
A5
A4
A3
A2
A1
A0
R/W
R1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
-
-
-
-
-
-
-
Bit7
Bit6 - 0
Nonuse
“1” is always read at read.
A6 - 0 (Address6 - 0)
Store slave address
In a slave mode it is compared with DAR register after address data reception, and
when in agreement, acknowledge is transmitted to a master.
Data Register(DAR)
Register
address
I2C Base Address + 0010h
Bit No
7
6
5
4
3
2
1
0
Bit field name D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
-
-
-
-
-
-
-
-
Bit7 - 0
D7 - 0 (Data7 - 0)
Store serial data
This is a data register for serial data transfer. The data is transferred from MSB. At
the time of data reception (TRX=0) the data output is set to “1”.
The writing side of this register is a double buffer. When the bus is in use (BB=1),
the write data is loaded to the register for serial transfer for every transfer. At the
time of read-out, the receiving data is effective only when INT bit is set because
the register for serial transfer is read directly at this time.
MB86296S <Coral-PA>
195
Specification Manual Rev0.1