MB86296 Datasheet, PDF (275/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
CDCP (Capture Data Count for PAL)
Register
address
CaputureBaseAddress + 4004h
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserve
d
BDCP
Reserve
d
VDCP
R/W
RX
RW
RX
RW
Initial value X
0x11B(283)
X
0x5A3(1443)
This register sets the count of data of the input video stream in PAL format.
Bit12-0
VDCP (Valid Data Count for PAL)
Sets count of data processed during valid period in PAL format. The setting value +1 is a
data number
Bit28-16
BDCP (Blanking Data Count for PAL)
Sets count of data processed during blanking period in PAL format. The setting value +1 is
a data number
VCS (Video Capture Status)
Register
address
CaputureBaseAddress + 08h
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserve
CE
R/W
RX
RW0
Initial value
X
00000
This register indicates the ITU-RBT656 SAV and EAV status.
To detect error codes, set NTSC/PAL in the VS bit of VCM. If NTSC is set, reference the
number of data in the capture data count register (CDCN). If PAL is set, reference the
number of data in the capture data counter register (CDCP). If the reference data does not
match the stream data , or undefined Fourth word of SAV/EAV codes are detected, bits 4 to
0 of the video capture status register (VCS) will be values as follows.
Bits 6-0 CE0 (Capture Error 0)
Bit0 1 : RBT.656 undefined error (Code Bit7)
Bit1 1 : RBT.656 undefined error (Code Bit7-4)
Bit2 1 : RBT.656 undefined error (Code Bit7-0)
Bit3 1 : RBT.656 long term H code error (SAV)
Bit4 1 : RBT.656 long term H code error (EAV)
MB86296S <Coral-PA>
265
Specification Manual Rev0.1
0 : true
0 : true
0 : true
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0 : true