MB86296 Datasheet, PDF (209/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
13.2.4 Display control register
DCM (Display Control Mode)
Register
address
DisplayBaseAddress + 00H (DisplayBaseAddress + 100H)
Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2
Bit field name CKS Reserved
SC
EEQ ODE Reserved Reserved SF ESY
R/W RW RW0
RW
RW RW RX RX RW RW
Initial value _{0 0}
001110(DCM)
111101(DCME)
00XX01
10
SYNC
RW
00
This register controls the display count mode. It is not initialized by a software reset. This register
is mapped to two addresses. The difference between the two registers is the format of the
frequency division rate setting (SC).
Bit 1 to 0
SYNC (Synchronize)
Set synchronization mode
X0 Non-interlace mode
10 Interlace mode
11 Interlace video mode
Bit 2
ESY (External Synchronize)
Sets external synchronization mode
0: External synchronization disabled
1: External synchronization enabled
Bit 3
SF (Synchronize signal format)
Sets format of synchronization (VSYNC, HSYNC) signals
0: Negative logic
1: Positive logic
Bit 7
EEQ (Enable Equalizing pulse)
Sets CCYNC signal mode
0: Does not insert equalizing pulse into CCYNC signal
1: Inserts equalizing pulse into CCYNC signal
Bit 13 to 8
SC (Scaling)
Divides display reference clock by the preset ratio to generate dot clock
Offset = 0
Offset = 100H
x00000 Frequency not divided
000000 Frequency not divided
x00001 Frequency division rate = 1/4 000001 Frequency division rate = 1/2
x00010 Frequency division rate = 1/6 000010 Frequency division rate = 1/3
X00011 Frequency division rate = 1/8 000011 Frequency division rate= 1/4
:
:
x11111 Frequency division rate = 1/64 111111 Frequency division rate = 1/64
MB86296S <Coral-PA>
199
Specification Manual Rev0.1