MB86296 Datasheet, PDF (49/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
transfer and pause it between bursts. This may be useful, for example, when doing PCI Master reads
from a client which takes time to pre-fetch more data for the next burst.
4.3 FIFO Transfers
Unlike Coral LQ/Coral LB there are no specific transfer mechanisms to write data into the display list
FIFO. A write to the FIFO interface occurs automatically when it is specified as a destination address
either for a PCI Slave Write or in a Burst Controller transfer. If this is not desired, and the main internal
bus should be used, then the Override FIFO Use register may be set. Under normal circumstances
there should be no need to use this feature.
As previously stated when the FIFO address is specified as the destination in the Burst Controller the
destination should not be incremented after each burst. This will not happen automatically and must
be specifically configured. In addition when writing to the FIFO using a PCI Slave Write the FIFO
address space is limited to 16 dwords (64 bytes). This means that a PCI Slave Write burst to the FIFO
must not be more than 16 dwords, otherwise data will be written to invalid locations for retries after 2
bursts of 8 dwords.
In normal mode when writing to the FIFO, data is written to the Geometry Engine FIFO from where it is
transferred either directly to the Draw Engine FIFO or to the Geometry Engine, depending on the
command. If the Geometry Engine is not in use then a direct write to the Draw Engine FIFO can be
accomplished by setting Cremson Mode (CM register).
When the burst controller is used to transfer data to the FIFO the rate of bursts us controlled using the
current FIFO status. When the FIFO is nearly full the next burst will not occur until data is processed
by the Geometry/Draw Engine. This guarantees that there will always be space for the next burst of
data. If this feature is not required then it can be disabled using the FIFO Burst Mode (FBM) register.
4.4 GPIO/Serial Interface
The Host Interface supports optional register mapped General Purpose IO (GPIO) and Serial Interface
functions.
4.4.1 GPIO
Depending on configuration there are up to 14 GPIO signals. 5 of these (GI0, GI1, GI2, GI3, GI4) are
inputs only. The remainder (BEN,SB,TC,BC,EE,ECS,ECK,EDI, EDO) may be either input or output. All
reset to GPIO inputs unless otherwise configured using the reset configuration mechanism to enable
the EEPROM/RGB input.
Operation of the GPIO is simply through the reading of the GPIO Data (GD) register for GPIO Inputs
and writing to this register (with write mask) for the GPIO Outputs. GPIO Inputs may be configured
selectively to trigger an external interrupt (via the interrupt status register (IST)) when they change
state (0->1 or 1->0 transition).
4.4.2 Serial Interface
A simple serial interface is available depending on configuration. This uses the EDI/EDO pins as serial
data input/output, the ECK as the serial clock output and SB as the serial interface strobe. The serial
data out signal may be tri-stated when not in use.
Up to 8 bits of data is shifted out/in based on the serial clock. This may be ¹/₁₆, ¹/₃₂, ¹/₆₄ or ¹/₁₂₈ of the
main internal clock. The clock polarity may be specified to be high/low and it may be gated when the
serial interface is inactive.
MB86296S <Coral-PA>
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Specification Manual Rev0.1