MB86296 Datasheet, PDF (211/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
DCE (Display Controller Enable)
Register
address
DisplayBaseAddress + 02H
Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name DEN
Reserved
L45E L23E L1E L0E
R/W RW
R0
RW RW RW RW
Initial value 0
0
0000
This register controls enabling the video signal output and display of each layer. Layer enabling is
specified in four-layer units to maintain backward compatibility with previous products.
Bit 0 L0E (L0 layer Enable)
Enables display of the L0 layer. The L0 layer corresponds to the C layer for previous
products.
0: Does not display L0 layer
1: Displays L0 layer
Bit 1 L1E (L1 layer Enable)
Enables display of the L1 layer. The L1 layer corresponds to the W layer for previous
products.
0: Does not display L1 layer
1: Displays L1 layer
Bit 2 L23E (L2 & L3 layer Enable)
Enables simultaneous display of the L2 and L3 layers. These layers correspond to the M
layer for previous products.
0: Does not display L2 and L3 layer
1: Displays L2 and L3 layer
Bit 3 L45E (L4 & L5 layer Enable)
Enables simultaneous display of the L4 and L5 layers. These layers correspond to the B
layer for previous products.
0: Does not display L4 and L5 layer
1: Displays L4 and L5 layer
Bit 15 DEN (Display Enable)
Enables display
0: Does not output display signal
1: Outputs display signal
MB86296S <Coral-PA>
201
Specification Manual Rev0.1