MB86296 Datasheet, PDF (206/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
13.2.3 Graphics memory interface registers
MMR (Memory I/F Mode Register)
Register
address
HostBaseAddress + FFFCH
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
*1 Reserved *1 *1
TRC TRP TRAS
RTS RAW
CL
R/W
R
R RW RW RW RW RW RW RW RW
RW
Initial value 0 0 Don’t care 1 0 00 0000 00 000 00 00 000 000 0 000
*1: Reserved
This register sets the mode of the graphics memory interface. A value must be written to this
register after a reset. (When default setting is performed, a value must also be written to this
register.) Only write once to this register; do not change the written value during operation.
This register is not initialized at a software reset.
Bit 2 to 0
CL (CAS Latency)
Sets the CAS latency. Write the same value as this field, to the mode register for SDRAM
011
CL3
010
CL2
Other than Setting disabled
the above
Bit 3
ASW (Attached SDRAM bit Width)
Sets the bit width of the data bus (memory bus width mode)
1
64 bit
0
32 bit
Bit 6 to 4
SAW (SDRAM Address Width)
Sets the bit width of the SDRAM address
001
15 bit BANK 2 bit ROW 13 bit COL 9 bit SDRAM
111
14 bit BANK 2 bit ROW 12 bit COL 9 bit SDRAM
110
14 bit BANK 2 bit ROW 12 bit COL 8 bit SDRAM
101
13 bit BANK 2 bit ROW 11 bit COL 8 bit SDRAM
100
12 bit BANK 1 bit ROW 11 bit COL 8 bit FCRAM
Other than Setting disabled
the above
Bit 9 to 7 RTS (Refresh Timing Setting)
Sets the refresh interval
000
Refresh is performed every 384 internal clocks.
111
Refresh is performed every 1552 internal clocks.
001 to 110 Refresh is performed every ‘64 × n’ internal clocks in the 64 to 384 range.
MB86296S<Coral-PA>
196
Specification Manual Rev0.1