MB86296 Datasheet, PDF (38/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
2.3.2 Video output interface
Pin name
DCKO
DCKI
HSYN
VSYN
CSYN
DE
GV
R7-0
G7-0
B7-0
XRE
AOR
AOG
AOB
COMR
COMG
COMB
VREF
VRO
Table 2-2 Video Output Interface Pins
I/O
Output
Input
I/O
I/O
Output
Output
Output
Output
Output
Output
Input
Analog Output
Analog Output
Analog Output
Analog
Analog
Analog
Analog
Analog
Description
Dot clock signal for display
Dot clock signal input
Horizontal sync signal output
Horizontal sync input <in external sync mode>
Vertical sync signal output
Vertical sync input <in external sync mode>
Composite sync signal output
Display enable period signal
Graphics/video switch
Digital picture (R) output. . These pins are multiplexed
MD53-46. These pins are available when XRE=0.
Digital picture (G) output. . These pins are multiplexed
MD45-3 8. These pins are available when XRE=0.
Digital picture (B) output. These pins are multiplexed MD37-
32 and DQM7-6. These pins are available when XRE=0.
Signal to switch between digital RGB output, capture signals
/memory bus (MD 63-32, DQM7-6)
Analog Signal (R) output
Analog Signal (G) output
Analog Signal (B) output
Analog (R) Compensation output
Analog (G) Compensation output
Analog (B) Compensation output
Analog Voltage Reference input
Analog Reference Current output
It is possible to output digital RGB when XRE = 0 (Memory bus = 32bit).
Additional setting of external circuits can generate composite video signal.
Synchronous to external video signal display can be performed.
Either mode which is synchronous to DCLKI signal or one which is synchronous to dot clock, as for
normal display can be selected.
Since HSYNC and VSYNC signals are set to input state after reset, these signals must be pulled up
LSI externally.
The GV signal switches graphics and video at chroma key operation. When video is selected, the
“Low” level is output.
AOR, AOG and AOB must be terminated at 75 ohm.
1.1 V is input to VREF. A bypass capacitor ( with good high-frequency characteristics ) must be
inserted between VREF and AVS.
COMR, COMG and COMB are tied to analog VDD via 0.1 uF ceramic capacitors.
VRO must be pulled down to analog ground by a 2.7 k ohm resister.
When not using DAC, it is possible to connect all of analog pins(AVD, AOUTR,G,B, ACOMPR,G,B,
VREF, VRO) to GND.
MB86296S<Coral-PA>
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Specification Manual Rev0.1