MB86296 Datasheet, PDF (50/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
The strobe signal has configurable polarity and may be active only for the first cycle of a transfer or the
complete transfer. It may also be disabled completely. Configured strobe settings may be overridden
on a transfer by transfer basis if required.
An interrupt may be generated when a transfer is complete.
4.5 Interrupt
The Coral PA MB86296 issues interrupt requests to the host CPU. The following interrupt triggers
may enabled/disabled using the Interrupt Mask Register (IMASK).
• Vertical synchronization detect
• Field synchronization detect
• External synchronization error detect
• Register update
• Drawing command error
• Drawing command execution end
• Internal Bus/FIFO Timeout
• Serial Interface transfer complete
• GPIO input change
• Burst Complete
• Transfer Complete
• Host Interface Fatal (PCI error)
• Address Error (invalid address accessed)
In addition the I²C interface can trigger an interrupt, but this is non-maskable through the IMASK
register.
By default the external interrupt is active low (PCI standard) and is open drain. If required it may be
configured to be active high using the Interrupt Polarity (IP) register.
Once an interrupt is detected by the host it can read the interrupt status register (IST) to determine the
source of the interrupt. The exception to this is the I²C interrupt. Once read the interrupt status register
must be cleared by writing 0 to the appropriate bit/bits (selective clearing is possible). Note that the
Burst Complete/Transfer Complete interrupts must be cleared by writing to the Burst Status (BST)
register.
4.5.1 Address Error Interrupt
Certain addresses are invalid depending on operation. For example the Burst Controller cannot
access the Host Interface internal registers. If an attempt is made to do this then the access will be
terminated and an Address Error Interrupt triggered.
MB86296S<Coral-PA>
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Specification Manual Rev0.1