MB86296 Datasheet, PDF (192/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
SIC (Serial Interface Control)
Register
address
HostBaseAddress + 00B0H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
CKD Reserved
Reserved
R/W
R0
RW
R0
R0
Initial value
0
00 0
0
0
0
000
This register provides control for the serial interface protocol and clock.
Bit 0
Bit 1
Bit 2
Bit 8
Bit 17 to
Bit 16
Bit 18
Bit 19
SL (Strobe Length)
If set to “0b” then the strobe signal is only active for one cycle at the start of a transfer.
Otherwise if set to “1b” it is active for the duration of the cycle. Note that this field may be
overridden for a single transaction using the FS/FSL fields in the SID register.
SP (Strobe Polarity)
If set to “0b” then strobe is active low. Otherwise if set to “1b” it is active high.
SD (Strobe Disable)
If set to “1b” then the serial interface strobe is disabled. Note that this field may be
overridden foe a single transaction using the FS field in the SID register.
DOE (Data Output Enable control)
If set to “0b” then the Data Out signal is driven permanently even when transactions are not
in progress. If set to “1b” then the Data Out is driven only during active cycles.
CKD (Clock Divisor)
This field specifies the serial interface clock divisor. The main system clock is divided down
by one of the following factors:
00b: 16
01b: 32
10b: 64
11b: 128
Based on a 133MHz internal clock these yield frequencies of approximately 8.3MHz,
4.1MHz, 2.0 MHz and 1.0MHz respectively.
CKG (Clock Gating)
When set to “1b” the serial interface clock is only active during active transfers. Otherwise if
set to “0b” it is active continuously. Note that the CKP field specifies the inactive value
when the clock is static.
CKP (Clock Polarity)
When set to “0b” data/strobe are clocked out on a falling edge of the serial interface clock
and data in is clocked in on the next falling edge. When clock gating is enabled (by setting
the CKG field) the static level is low.
When set to “1b” data/strobe are clocked out on a rising edge of the serial interface clock
and data in is clocked in on the next falling edge. When clock gating is enabled (by setting
the CKG field) the static level is high.
MB86296S<Coral-PA>
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Specification Manual Rev0.1