MB86296 Datasheet, PDF (47/352 Pages) Fujitsu Component Limited. – PCI Graphics Controller Specification

FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL
A transfer can be any number of dwords from 1 to 16777215 (2²⁴-1) dwords, split up into a number of
individual bursts of size from 1 to 8 dwords. If the transfer size is not an integer multiple of the burst
size then the final burst of the transfer will be less than the configured burst size. A transfer is from a
source address to a destination address with the source/destination being in either PCI or Coral PA
data space as appropriate to the transfer mode. After each burst of a transfer the source and/or the
destination address may be incremented (or not) by the burst size enabling transfers both to/from
memory and also FIFO-like sources/destinations. Note that when writing to the display list FIFO, the
destination address should be configured to not increment between bursts.
4.2.1 Transfer Modes
There are 6 transfer modes configurable through the Burst Setup Register (BSR). These are:
Mode
Function
000b Slave Mode PCI to Coral PA. In this mode a PCI master writes bursts of data directly into a
temporary buffer from where it is transferred to the destination address by the Burst
Controller. While this can also be accomplished using simple PCI Slave writes there are
benefits in using this mode when transferring large quantities of data. For a normal PCI
write the Coral PA PCI slave interface is blocked until the write to the destination address
has completed. Depending on the destination there may be some delay in doing this. Using
the burst controller the data is transferred out of the PCI interface into the temporary buffer
from where it is transferred to the destination. In this case the PCI slave interface is quickly
cleared and so other operations can take place or the next burst can be written in.
001b Slave Mode Coral PA to PCI. In this mode the burst controller reads data from a Coral PA
internal address into its temporary buffer and then waits for the data to be read using a PCI
slave read from this buffer’s address. While this can also be accomplished using simple
PCI Slave reads there are benefits in using this mode when transferring large quantities of
data. A normal PCI read will typically be accomplished by a PCI read request followed by a
retry to fetch the data. Using this mode the burst controller can be used to automatically
fetch the next data to be read. Depending on internal latencies this should reduce the
number of retries.
010b Coral PA to Coral PA. In this mode data is read from a source address internal to Coral PA
into a temporary buffer, from where it is written to a destination, also internal to Coral PA.
An example of where this mode may be used is to transfer display list data from graphics
memory to the display list FIFO.
011b Reserved.
100b PCI to Coral PA (PCI Master read). In this mode the source address is in PCI data space
and the destination address internal to Coral PA. For each burst of the transfer “burst size”
dwords of data are read as a PCI Master read into a temporary buffer, from where they are
written to the internal destination address. An example of where this mode will be used is
display list transfer to the FIFO/graphics memory.
101b Coral PA to PCI (PCI Master write). In this mode the source address is internal to Coral PA
and the destination address is in PCI data space. For each burst of the transfer “burst size”
dwords of data are fetched from an internal address into a temporary buffer, from where
they are written to the destination address using a PCI master write. An example of where
this mode may be used is to transfer graphics memory data to external PCI memory.
MB86296S <Coral-PA>
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Specification Manual Rev0.1