MC68HC08BD24 Datasheet, PDF (98/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

7.8 SIM Registers
The SIM has three memory mapped registers. Table 7-5 shows the
mapping of these registers.
Table 7-5. SIM Registers Summary
Address
$FE00
$FE01
$FE03
Register
SBSR
SRSR
SBFCR
Access Mode
User
User
User
7.8.1 SIM Break Status Register (SBSR)
The SIM break status register contains a flag to indicate that a break
caused an exit from stop or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
Note
Reset: 0
0
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
R = Reserved
Figure 7-18. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
Technical Data
98
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor