MC68HC08BD24 Datasheet, PDF (202/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

15.6 Port D
Port D is an 7-bit special-function port that shares one of its pins with the
sync processor and two of its pins with the DDC12AB module.
NOTE: PTD1 and PTD0 are 3.3V pins.
15.6.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight
port D pins.
Address:
Read:
Write:
Reset:
Alternate
Function:
$0003
Bit 7
0
6
PTD6
—
5
4
3
2
1
PTD5 PTD4 PTD3 PTD2 PTD1
Unaffected by reset
—
CLAMP DDCSCL DDCSDA —
Bit 0
PTD0
—
= Unimplemented
Figure 15-12. Port D Data Register (PTD)
PTD6–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
CLAMP — Sync Processor Clamp pulse output pin
The PTD4/CLAMP pin is the sync processor clamp pulse output pin.
When the CLAMPE bit in the port D configuration register (PDCR) is
clear, the PTD4/CLAMP pin is available for general-purpose I/O. See
15.6.3 Port D Options.
Technical Data
202
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor