MC68HC08BD24 Datasheet, PDF (204/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 15-14. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-6 summarizes
the operation of the port D pins.
Table 15-6. Port D Pin Functions
PTDPUE Bit
0
DDRD Bit
0
PTD Bit
X
I/O Pin Mode
Input, Hi-Z⁽²⁾
Accesses to DDRD
Read/Write
DDRD7–DDRD0
Accesses to PTD
Read
Pin
Write
PTD7–PTD0⁽³⁾
X
1
X
Output
DDRD7–DDRD0 PTD7–PTD0 PTD7–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Technical Data
204
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor