MC68HC08BD24 Datasheet, PDF (90/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt may take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared). (See Figure
7-9. Interrupt Processing.)
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 7-10
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
LDA #$FF
BACKGROUND ROUTINE
INT1
PSHH
PULH
RTI
INT1 INTERRUPT SERVICE ROUTINE
Technical Data
90
INT2
PSHH
PULH
RTI
INT2 INTERRUPT SERVICE ROUTINE
Figure 7-10. Interrupt Recognition Example
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor