MC68HC08BD24 Datasheet, PDF (183/244 Pages) Motorola, Inc – HCMOS Microcontroller Unit

CPW[1:0] — Clamp Pulse Width
The CPW1 and CPW0 bits are used to select the output clamp pulse
width. Reset clears these bits, selecting a default clamp pulse width
between 0.33µs and 0.375µs. These bits always read as Zeros.
Table 14-7. Clamp Pulse Width
CPW1
0
0
1
1
CPW0
0
1
0
1
Clamp Pulse Width
0.33µs to 0.375µs
0.5µs to 0.542µs
0.75µs to 0.792µs
2µs to 2.042µs
14.6.4 Hsync Frequency Registers (HFRs)
This register pair contains the 13-bit Hsync frequency count value and
an overflow bit.
Address:
Read:
Write:
Reset:
$0043
Bit 7
HFH7
0
6
HFH6
0
5
HFH5
0
4
HFH4
0
3
HFH3
0
2
HFH2
0
1
HFH1
0
Figure 14-7. Hsync Frequency High Register
Address: $0044
Bit 7
6
5
Read: HOVER
0
0
Write:
Reset: 0
0
0
= Unimplemented
4
HFL4
3
HFL3
2
HFL2
1
HFL1
0
0
0
0
Figure 14-8. Hsync Frequency Low Register
Bit 0
HFH0
0
Bit 0
HFL0
0
MC68HC08BD24 — Rev. 1.1
Freescale Semiconductor
Technical Data
183